The _________ is a small cache memory associated with the instruction fetch stage of the pipeline.

The _________ is a small cache memory associated with the instruction fetch stage of the pipeline.

A. dynamic branch
B. loop table
C. branch history table
D. flag


Answer: C

A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions in sequence.

A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions in sequence.

A. loop buffer
B. delayed branch
C. multiple stream
D. branch prediction


Answer: A

_______ is a pipeline hazard.

_______ is a pipeline hazard.

A. Control
B. Resource
C. Data
D. All of the above


Answer: D

The ________ determines the opcode and the operand specifiers.

The ________ determines the opcode and the operand specifiers.

A. decode instruction
B. fetch operands
C. calculate operands
D. execute instruction


Answer: A

The _________ contains a word of data to be written to memory or the word most recently read.

The _________ contains a word of data to be written to memory or the word most recently read.

A. MAR
B. PC
C. MBR
D. IR


Answer: C

________ are bits set by the processor hardware as the result of operations.

________ are bits set by the processor hardware as the result of operations.

A. MIPS
B. Condition codes
C. Stacks
D. PSWs


Answer: B

____ is a design principle employed in designing the PDP-10 instruction set.

____ is a design principle employed in designing the PDP-10 instruction set.

a. Orthogonality
b. Completeness
c. Direct addressing
d. All of the above


Answer: All of the above