Some character sets use 16-bit characters. The would be loaded by which MIPS command?

Some character sets use 16-bit characters. The would be loaded by which MIPS command? 

A. LBU
B. LHU
C. LB
D. LW


Answer: B. LHU

To move a unicode character from memory to a register, which MIPS instruction should be used?

To move a unicode character from memory to a register, which MIPS instruction should be used?

A. lwu
B. lbu
C. lw
D. lh
E. lhu
F. lb


Answer: E. lhu

The difference between ASCII and Unicode is

The difference between ASCII and Unicode is

A. Unicode is used by Java and ASCII is used by Microsoft.
B. Apple only uses ASCII
C. Unicode represents up to 256 characters, and ASCII represents up to 65536 characters.
D. ASCII is used in Java and unicode is used by Microsoft
E. Unicode can represent more characters than ASCII.
F. ASCII represents up to 256 characters, and Unicode represents up to 65536 characters.
G. ASCII is popular in foreign languages and Unicode is not


Answer:

E. Unicode can represent more characters than ASCII.
F. ASCII represents up to 256 characters, and Unicode represents up to 65536 characters.

Storage and use of decimal numbers for computation in computers is

Storage and use of decimal numbers for computation in computers is

A. Unpopular because the standards are complicated.
B. A good idea years ago, but no longer necessary because of cheap memory.
C. Never used anymore.
D. Sometimes useful in financial applications.
E. Inefficient because numbers are more accurately represented in binary
F. Becoming more likely with the advent of multicore processors
G. More difficult to implement and consumes more memory than needed.


Answer:

D. Sometimes useful in financial applications.
G. More difficult to implement and consumes more memory than needed.

The MIPS instruction(s) used to load a 32-bit register with data which is hard-coded into the program is/are

The MIPS instruction(s) used to load a 32-bit register with data which is hard-coded into the program is/are

A. ori, lui
B. mov
C. mfhi, mflo
D. addui
E. lui, ori
F. ld32
G. ld, la


Answer:


A. ori, lui
E. lui, ori

Which MIPS registers should not be used by the programmer?

Which MIPS registers should not be used by the programmer?

A. $at
B. $sp
C. $v0, $v1
D. $ra


Answer: A. $at

A disadvantage of recursion is that it can consume a lot of

A disadvantage of recursion is that it can consume a lot of

A. Registers
B. Stack space
C. Execution cycles
D. Heap memory
E. Memory on the stack.
F. Cache memory.
G. Main memory.


Answer:

B. Stack space
E. Memory on the stack.

Which register is used in allocation of memory on the heap?

Which register is used in allocation of memory on the heap?

A. $fp
B. $sp
C. The global pointer
D. The OS pointer.
E. $gp
F. $ra
G. The heap pointer.


Answer:

C. The global pointer
E. $gp

What MIPS registers bound the local variable storage area for a subroutine?

What MIPS registers bound the local variable storage area for a subroutine?

A. $gp and $fp
B. The stack pointer and the frame pointer.
C. $fp and $sp
D. $ra and $sp
E. The stack pointer and the return address.
F. The frame pointer and the global pointer.
G. $sp and $gp


Answer:

B. The stack pointer and the frame pointer.
C. $fp and $sp

In a recursive procedure

In a recursive procedure 

A. $t register values must be preserved
B. Local storage must be allocated on the stack.
C. $ra does not have to be preserved.
D. JAL is never used.


Answer: B. Local storage must be allocated on the stack.

If subroutine A calls subroutine B

If subroutine A calls subroutine B

A. Subroutine B must preserve $ra.
B. Neither subroutine needs to preserve $ra; it is automatically saved.
C. Subroutine A is a non-leaf subroutine.
D. Subroutine A must preserve $ra.
E. There is no convention as long as the code works.
F. No stack space is needed.
G. Subroutine A is a leaf routine.

Answer:


C. Subroutine A is a non-leaf subroutine.
D. Subroutine A must preserve $ra.

To adjust the stack pointer to make room for three 32-bit values, the correct instruction is

To adjust the stack pointer to make room for three 32-bit values, the correct instruction is

A. addi $sp, $sp, 0x0012
B. addi $sp, $sp, 0xc
C. addi $sp, $sp, 0xfff4
D. addi $sp, $sp, -12
E. addi $sp, $sp, 3
F. addi $sp, $sp, -3
G. addi $sp, $sp, 12


Answer:


C. addi $sp, $sp, 0xfff4
D. addi $sp, $sp, -12

The jal instruction is unique because it also

The jal instruction is unique because it also

A. Does not update the program counter
B. Checks the $ra before it branches
C. Writes to the $ra register
D. Always executes (i.e., it is not conditional)
E. Copies $pc to $ra
F. Operates on four registers
G. Resets the $pc register


Answer:

C. Writes to the $ra register
E. Copies $pc to $ra

Which instruction is commonly used for a subroutine call?

Which instruction is commonly used for a subroutine call?

A. bne
B. jal
C. beq
D. jr $ra
E. j
F. call
G. jump and link


Answer:

B. jam
G. jump and link

A jump table in combination with the ____ instruction can be used to implement a case or switch statement.

A jump table in combination with the ____ instruction can be used to implement a case or switch statement. 

A. jeqz
B. jump register
C. jal
D. beq
E. jr
F. j
G. bne


Answer:

B. jump register
E. jr

Which signed byte has the smallest value?

Which signed byte has the smallest value?

A. 0x80
B. 0x0f
C. 0x81
D. 0x87
E. 0x01
F. 0x7f
G. 0x00


Answer:

A. 0x80
C. 0x81

A good argument for MIPS not having a hardware instruction for "branch on less than" is:

A good argument for MIPS not having a hardware instruction for "branch on less than" is: 

A. It can be produced from two simple instructions
B. The space on the silicon to implement the instruction would reduce the size of cache.
C. The complexity of the instruction would stretch the clock cycle for many more, less complicated instructions.
D. Because of its complexity the instruction would sink more power causing the chip to heat up too much.
E. The MIPS assembler can do it.
F. It gives students something to think about.
G. It is a pseudo instruction.


Answer: A. It can be produced from two simple instructions
C. The complexity of the instruction would stretch the clock cycle for many more, less complicated instructions.

Register $t0 contains 0xFFFFFFFF and register $t1 contains 0x00000000. Which instruction will see $t0 as greater than $t1?

Register $t0 contains 0xFFFFFFFF and register $t1 contains 0x00000000. Which instruction will see $t0 as greater than $t1?

A. salt
B. sltu
C. sltu $s0, $t0, $t1
D. slt $s0, $t1, $t0
E. beq $t0, $t1, label
F. slti
G. slt $s0, $t0, $t1


Answer:

B. sltu
C. sltu $s0, $t0, $t1

To create all conditions for branches, MIPS uses which set of instructions?

To create all conditions for branches, MIPS uses which set of instructions?

A. slt, slti, beq, bne, and the $zero register
B. The $0 register, slt/slti and bne/beq
C. beqz, addi, add, sub
D. sll, srl, beq, bne, and the $zero register
E. j, jne, jeq, jal and the $zero register
F. blt, bgt, blte, bgte
G. blt, bgt, lgbt


Answer:

A. slt, slti, beq, bne, and the $zero register
B. The $0 register, slt/slti and bne/beq

A sequence of instructions without branches in the middle is called a(n)

A sequence of instructions without branches in the middle is called a(n)

A. Basic block
B. Basic code block
C. Data
D. Code segment
E. Text
F. Subroutine
G. Module


Answer:

A. Basic block
B. Basic code block

A conditional branch is appropriate for

A conditional branch is appropriate for

A. Transferring control to a different part of the program.
B. A loop
C. Checking for a zero denominator.
D. Shifting a register right or left
E. Termination of a program
F. Jumping to a new location.
G. A subroutine call


Answer:

B. A loop
C. Checking for a zero denominator.

The Program Counter contains the address of the next instruction to be executed. Which MIPS instruction would affect the value of the PC?

The Program Counter contains the address of the next instruction to be executed. Which MIPS instruction would affect the value of the PC?

A. ADDI
B. BEQ or BNE
C. J
D. SW
E. LW
F. IF
G. GO


Answer:

B. BEQ or BNE
C. J

MIPS conditional branch instructions require the comparison of

MIPS conditional branch instructions require the comparison of

A. rs and rt
B. rs and rd
C. Two registers
D. A combination of three registers
E. One register to zero
F. rt and rd
G. A register and an immediate value


Answer:

A. rs and rt
C. Two registers

The BEQ and BNE instructions are

The BEQ and BNE instructions are

A. Offsets
B. Conditional branches
C. Jumps
D. GOTOs
E. Unconditional branches
F. Not jumps
G. Labels


Answer:

B. Conditional branches
F. Not jumps

How many Branch instructions does the MIPS processor recognize?

How many Branch instructions does the MIPS processor recognize?

A. Three (BNE, BEQ, BEZ)
B. 4
C. 2
D. Four (BNE, BEQ, BEZ, BNZ)
E. One (BRN)
F. 3
G. Two (BNE, BEQ)


Answer:

C. 2
G. Two (BNE, BEQ)

What operation wound combine 0x80000000 with 0xC0000000 to produce 0x40000000?

What operation wound combine 0x80000000 with 0xC0000000 to produce 0x40000000?

A. NAND
B. Exclusive OR
C. NOR
D. XOR
E. Inclusive OR
F. XAND
G. NOT

Answer:

B. Exclusive OR
D. XOR

Which is not a field in the MIPS instruction format?

Which is not a field in the MIPS instruction format?

A. rt
B. precision
C. shamt
D. funct
E. rs
F. op
G. instruction length00

Answer:

B. precision
G. instruction length00

The shamt field in the MIPS instruction is use for which instruction?

The shamt field in the MIPS instruction is use for which instruction?

A. XOR
B. SLLI
C. Branch
D. SRL
E. NOR
F. SLL
G. SLT

Answer:


D. SRL
F. SLL

Which instruction does MIPS not have?

Which instruction does MIPS not have?

A. Shift left
B. XOR
C. Shift right
D. ADDI
E. ADD
F. NOT
G. SUBI


Answer:


F. NOT
G. SUBI

How many bits in a MIPS instruction are allocated for immediate data

How many bits in a MIPS instruction are allocated for immediate data

A. Eight
B. 15
C. Sixteen
D. Twenty-four
E. 12
F. 16
G. Ten


Answer:

C. Sixteen
F. 16

To refer to each of the 32 MIPS processor register, an instruction needs

To refer to each of the 32 MIPS processor register, an instruction needs

A. Six bits
B. Three bits
C. 5 bits
D. 16 bits
E. Five bits
F. 32 bits
G. Four bits

Answer:

C. 5 bits
E. Five bits

The easiest conversion is from

The easiest conversion is from

A. hexadecimal to decimal
B. Decimal to Hexadecimal.
C. Decimal to Binary
D. binary to decimal
E. Binary to hexadecimal
F. Hexadecimal to binary.
G. positive to negative


Answer:

E. Binary to hexadecimal
F. Hexadecimal to binary.

Which instruction field is 6-bits long?

Which instruction field is 6-bits long?

A. Shamt
B. Rs
C. Fct Code
D. Rd
E. Op Code
F. Rt
G. Imm


Answer:

C. Fct Code
E. Op Code

All MIPS instructions have

All MIPS instructions have

A. Embedded memory addresses
B. A function code
C. A byte which indicates how long it is
D. An Operations Code field
E. Immediate data
F. A field for the Rd register
G. Length of 32 bits


Answer:


D. An Operations Code field
G. Length of 32 bits

What is the native, binary form of instructions used by the processor?

What is the native, binary form of instructions used by the processor? 

A. Machine instructions
B. Assembly language
C. Intermediate Language
D. Machine language
E. Assembly code.
F. Source code.
G. Byte Code


Answer:

A. Machine instructions
D. Machine language

In biased notation, the most negative value is

In biased notation, the most negative value is

A. 0x10000000
B. 0x00000000
C. 0xfffe
D. 0x0001
E. 0xFFFFFFFF
F. ox80000000
G. 0x0000


Answer:

B. 0x00000000
G. 0x0000

The problem with one's-complement representation of negative numbers was

The problem with one's-complement representation of negative numbers was

A. There were more positive numbers than negative
B. There were two zeroes
C. It confused the programmers
D. There were more negative numbers than positive
E. It was hard to recognize the difference between positive and negative numbers
F. It was more difficult to implement than twos-complement
G. There is no such thing as one's complement.


Answer:

B. There were two zeroes
F. It was more difficult to implement than twos-complement

The interface between low-level hardware and software is called

The interface between low-level hardware and software is called

A. The interpreter.
B. Interrupt subsystem.
C. Cache.
D. The instruction set architecture
E. The operating system
F. Instruction-level parallelism


Answer: D. The instruction set architecture

Which signed number is the same as 0x80?

Which signed number is the same as 0x80?

A. 0x80FFFFFF
B. 0xFFFFFF80
C. 0x807FFFFF
D. 0xff08
E. 0xff80
F. 0x7f80
G. 0x7FFFFF80


Answer:

B. 0xFFFFFF80
E. 0xff80

Which set of binary numbers are the two's complement of each other?

Which set of binary numbers are the two's complement of each other?

A. 0101 1011
B. 00000001 11111111
C. 00000011 11111100
D. 00000001 00000000
E. 1111 0000
F. 00000000 11111111
G. 1010 0101


Answer:

A. 0101 1011
B. 00000001 11111111

In binary, subtracting a large positive number from a small positive number produces

In binary, subtracting a large positive number from a small positive number produces

A. an underflow condition
B. an overflow condition
C. A one in the left bit of the result
D. a zero in the leftmost bit of the result


Answer: C. A one in the left bit of the result

Negative numbers can be represented in binary

Negative numbers can be represented in binary

A. F
B. T


Answer: B. T

In a 32-bit MIPS instruction, the location of bit 0 (the least significant bit)

In a 32-bit MIPS instruction, the location of bit 0 (the least significant bit)

A. Varies by memory manufacturer
B. T=Is on the left and middle
C. Is in the middle and the right
D. is on the right
E. Depends on the instruction
F. The farthest right bit'
G. Is on the left


Answer:


D. is on the right
F. The farthest right bit'

Which 16-bit hex value would represent a negative number?

Which 16-bit hex value would represent a negative number?

A. 0X7fff
B. 0x100f
C. 0x0001
D. 0x0fff
E. 0x7777
F. 0x8001
G. 0xffff


Answer:


F. 0x8001
G. 0xffff

Immediate operands are

Immediate operands are

A. Data located in registers
B. Data located in cache
C. Data located in the instruction itself
D. Data encoded in the instruction
E. Calculated from register values
F. Obtained by adding an offset to a register
G. Data located in main memory


Answer:

C. Data located in the instruction itself
D. Data encoded in the instruction

The typical MIPS immediate instruction (e.g., ADDI, SUBI) contains references to how many registers?

The typical MIPS immediate instruction (e.g., ADDI, SUBI) contains references to how many registers?

A. Four
B. 2
C. One
D. Two
E. None
F. Three
G. Five


Answer:

B. 2
D. Two

The typical MIPS register-to-register arithmetic instruction (e.g., ADD, SUB) contains references to how many registers?

The typical MIPS register-to-register arithmetic instruction (e.g., ADD, SUB) contains references to how many registers?

A. One
B. Three
C. Five
D. None
E. Two
F. Four
G. 3


Answer:


B. Three
G. 3

If four-byte alignment is required, at which address could an integer not be stored?

If four-byte alignment is required, at which address could an integer not be stored?

A. 0x00410AA4
B. 0x00410003
C. 0x00ABFEDC
D. 0x00418210
E. 0x0041791C
F. 0x00123454
G. 0x0041000E


Answer:

B. 0x00410003
G. 0x0041000E

Memory alignment means

Memory alignment means

A. All eight bits of a byte must reside on the same chip
B. 4-byte words must begin on 4-byte boundaries
C. More than one word can be read from memory at once
D. Dynamic RAM is faster than Static RAM
E. The bottom two bits of a MIPS instruction address must be zero
F. Memory chips must be placed next to each other
G. Similar data items are placed next to each other in memory

Answer:


B. 4-byte words must begin on 4-byte boundaries
E. The bottom two bits of a MIPS instruction address must be zero

What is the reason that addresses of integer data stored in main memory must have the last two bits set to 0?

What is the reason that addresses of integer data stored in main memory must have the last two bits set to 0?

A. The data bus is only 30 bits wide
B. The cache can operate more efficiently
C. There is an alignment restriction
D. Words must be eight-byte aligned
E. Word data must be four-byte aligned
F. Data can be located anywhere in memory.
G. Memory is scarce and must be used efficiently


Answer:


C. There is an alignment restriction
E. Word data must be four-byte aligned

What is the generic name of instructions which move data between the processor and memory?

What is the generic name of instructions which move data between the processor and memory?

A. Cache control
B. Data transfer
C. Arithmetic instructions
D. Branch instructions
E. Memory Control
F. Register-register
G. Data transfer instructions


Answer:


B. Data transfer
G. Data transfer instructions

In MIPS, data is moved to and from memory using

In MIPS, data is moved to and from memory using

A. Branch instructions
B. Load and Store instructions
C. I-type add and subtract instructions
D. Data transfer instructions
E. R-type add and subtract instructions
F. Value instructions
G. Argument instructions

Answer:


B. Load and Store instructions
D. Data transfer instructions

In the instruction "add $s0, $s1, $s2", $s1 and $s2 are

In the instruction "add $s0, $s1, $s2", $s1 and $s2 are

A. Operands
B. Immediate values
C. Memory locations
D. Bytes
E. Arguments
F. Registers
G. Outputs

Answer:


A. Operands
F. Registers

Which language will have the most lines of code to implement a sort algorithm?

Which language will have the most lines of code to implement a sort algorithm?

A. Python
B. Assembly code
C. C++
D. C#
E. Pascal
F. Java
G. MIPS Assembly Language


Answer:


B. Assembly code
G. MIPS Assembly Language

The C code "d = a - e" could be represented in MIPS assembly as

The C code "d = a - e" could be represented in MIPS assembly as

A. sub $t0, $t1, $t2 where d=$t0, a=$t2 and e=$t1
B. SUB a, e, d
C. sub $t0, $t1, $t2 where d=$t0, a=$t1 and e=$t2
D. SUB d, a, e
E. SUB d, e, a
F. sub $t0, $t2, $t1 where d=$t0, a=$t1 and e=$t2
G. d SUB a, e


Answer:


C. sub $t0, $t1, $t2 where d=$t0, a=$t1 and e=$t2
D. SUB d, a, e

The The contents of a memory location whose address is contained in register $s1 may be expressed as:

The The contents of a memory location whose address is contained in register $s1 may be expressed as:

A. Regs[$s1]
B. 4($s1)
C. Mem[Regs[$s1]]
D. Regs[Mem[$s1]]
E. $s1
F. Mem[$s1]


Answer: C.Mem[Regs[$s1]]

The fastest access to data is via

The fastest access to data is via

A. Registers
B. Disk
C. Cache
D. Main memory


Answer: A. Registers

The vocabulary of the CPU is the

The vocabulary of the CPU is the

A. Instruction set
B. Organization
C. Datapath
D. Description
E. Architecture
F. Programs
G. Instructions


Answer:

A. Instruction set
G. Instructions

What is the vocabulary of commands understood by the processor?

What is the vocabulary of commands understood by the processor?

A. The instructions
B. The instruction set architecture
C. The intermediate code
D. The instruction set
E. The assembly language
F. The byte code
G. The binary executable


Answer:


A. The instructions
D. The instruction set

Execution time is the only valid measure of performance

Execution time is the only valid measure of performance

A. F
B. T


Answer: B. T

When comparing the performance of different operating systems on different processors, instruction count can be ignored

When comparing the performance of different operating systems on different processors, instruction count can be ignored

A. T
B. F


Answer: B. F

Energy efficiency can be an important performance goal

Energy efficiency can be an important performance goal

A. T
B. F


Answer: A. T

Idling computers consume a tiny fraction of the power they use at full load

Idling computers consume a tiny fraction of the power they use at full load

A. T
B. F


Answer: B. F

Adding more cores to a processor will not improve performance if

Adding more cores to a processor will not improve performance if

A. The cores are all the same size
B. The program only contains steps which must be executed in sequence
C. Several parts of the problem can be worked on at once
D. No part of the program can be done in parallel with another part
E. More cores means more power consumption
F. Program execution speed depends on the clock frequency
G. The program can be broken into multiple parallel paths


Answer:


B. The program only contains steps which must be executed in sequence
D. No part of the program can be done in parallel with another part

Multiple SPEC ratios are combined using

Multiple SPEC ratios are combined using

A. The geometric mean
B. Logarithms
C. The arithmetic mean
D. Covariance


Answer: A. The geometric mean

To get a better picture of CPU performance

To get a better picture of CPU performance

A. The industry has standards for honesty and integrity in testing
B. Tests are run multiple times
C. Customers are allowed to assess CPU performance on their own
D. A suite of benchmark programs is used


Answer: D. A suite of benchmark programs is used

SPEC benchmarks are

SPEC benchmarks are

A. Unreliable because testers cheat
B. Obsolete because of recent innovations in chip design
C. A long-standing set of standard test programs
D. A brand new way to measure performance


Answer: C. A long-standing set of standard test programs

One of Hennessy and Patterson design rules is

One of Hennessy and Patterson design rules is

A. Make the instruction set as compact as possible
B. Make the common case fast
C. Memory is cheap
D. Get the product to market as soon as possible


Answer: B. Make the common case fast

Which of the following does not result in performance gains?

Which of the following does not result in performance gains?

A. Memory Hierarchies
B. Prediction
C. Lower voltage requirements
D. Pipelining


Answer: C. Lower voltage requirements

The big problem with the switch to multi-processing is that

The big problem with the switch to multi-processing is that

A. More heat-sinking is required
B. Performance measures are very different
C. The chips are more difficult to manufacture
D. Programmers have to think differently


Answer: D. Programmers have to think differently

Which is not a factor in CPU power consumption?

Which is not a factor in CPU power consumption?

A. Capacitive load
B. Instruction length
C. Supply voltage
D. Switching frequency


Answer: B. Instruction length

An increase in which of the following has the greatest effect on CPU power consumption

An increase in which of the following has the greatest effect on CPU power consumption

A. Capacitive load
B. Voltage
C. CPI
D. Switching frequency


Answer: B. Voltage

The primary technology used in fabricating computer chips is

The primary technology used in fabricating computer chips is

A. Tunneling
B. Complementary Metal Oxide Semiconductor (CMOS)
C. Three-dimensional printing
D. NAND flash



Answer: B. Complementary Metal Oxide Semiconductor (CMOS)

The main reason for the shift from uniprocessors to multi-core processors was

The main reason for the shift from uniprocessors to multi-core processors was

A. Personal mobile devices
B. The internet
C. The power wall
D. iPhones and iPads


Answer: C. The power wall

What translates a symbolic representation of computer instructions into binary so that the processor can execute the instructions?

What translates a symbolic representation of computer instructions into binary so that the processor can execute the instructions?

A. A converter
B. An assembler.
C. A compiler.
D. A translator.


Answer: B. An assembler.

If Program B on Machine B has fewer instructions than Program A on Machine A, it will run faster unless

If Program B on Machine B has fewer instructions than Program A on Machine A, it will run faster unless

A. Machine B doesn't have more cores.
B. Machine A has more memory.
C. Machine B's CPI isn't too large.
D. Machine B's clock speed isn't too high.


Answer: C. Machine B's CPI isn't too large.

The measure of the frequency of instructions of certain types across a program or multiple programs is the

The measure of the frequency of instructions of certain types across a program or multiple programs is the

A. Average CPI.
B. Program count.
C. Instruction mix.
D. Instruction set architeture.


Answer: C. Instruction mix.

How can a CPI of less than 1.0 be achieved?

How can a CPI of less than 1.0 be achieved?

A. Executing fewer instructions
B. Shorter instructions
C. Faster clock cycle time
D. Issuing multiple instructions per clock cycle


Answer: D. Issuing multiple instructions per clock cycle

The compiler can affect CPI

The compiler can affect CPI

A. F
B. T


Answer: B. T

If two machines run the same program and the machines' instruction sets have the same CPI, on what does execution time depend

If two machines run the same program and the machines' instruction sets have the same CPI, on what does execution time depend

A. Number of memory accesses
B. Clock cycle time
C. Cache size
D. The paging algorithm


Answer: B. Clock cycle time

Machine B is 50% faster than Machine A. B runs a program in 12 seconds. How long does it take A to run it

Machine B is 50% faster than Machine A. B runs a program in 12 seconds. How long does it take A to run it

A. Ten seconds
B. Nine seconds
C. 12 seconds
D. 18 seconds
E. 15 seconds
F. Eighteen seconds
G. Eight seconds


Answer:

D. 18 seconds
F. Eighteen seconds

Two computers executing the same instructions complete the task in different amounts of time. What must be the case?

Two computers executing the same instructions complete the task in different amounts of time. What must be the case?

A. Cycles per instruction are different
B. A mistake was made
C. One machine did more work than the other
D. Clock speeds are different


Answer: D. Clock speeds are different

Cycles Per Instruction (CPI) must be an integer value

Cycles Per Instruction (CPI) must be an integer value

A. F
B. T


Answer: A. F

The execution time of a program is related to

The execution time of a program is related to

A. The number of instructions times the clock speed.
B. The average CPI times the clock speed.
C. The number of instructions times the average CPI for the program.
D. The number of instructions divided by the clock speed


Answer: C. The number of instructions times the average CPI for the program.

The average number of clock cycles per instruction (CPI) in a program is an integer value

The average number of clock cycles per instruction (CPI) in a program is an integer value

A. F
B. T


Answer: A. F

Which results in better performance?

Which results in better performance?

A. Decreased CPI
B. Increased CPI
C. Decreased clock rate
D. Increased instruction count


Answer: A. Decreased CPI

Which of the following is a typical challenge for computer designers

Which of the following is a typical challenge for computer designers

A. Building machines which appeal to both men and women.
B. Balancing the size of memory and the weight of the machine.
C. The tradeoff between the number of clock cycles needed for a program to execute and the length of each clock cycle.
D. Staying awake during the boring parts of class.


Answer: C. The tradeoff between the number of clock cycles needed for a program to execute and the length of each clock cycle.

On which of the following does execution time not depend?

On which of the following does execution time not depend?

A. Average cycles per instruction
B. Number of instructions executed
C. Clock cycle time
D. Amount of system memory


Answer: D. Amount of system memory

Machine A is 4 times as fast as machine B. B runs an application in 30 seconds. How fast will A run it?

Machine A is 4 times as fast as machine B. B runs an application in 30 seconds. How fast will A run it?

A. 120 seconds
B. 7.5 seconds
C. 90 seconds
D. 10 seconds


Answer: B. 7.5 seconds

Applications running on servers are particularly sensitive to

Applications running on servers are particularly sensitive to

A. the amount of main memory
B. disk performance
C. I/O time
D. cache memory


Answer: C. I/O time

The CPU time spent in the operating system performing tasks on behalf of a program is called

The CPU time spent in the operating system performing tasks on behalf of a program is called

A. user CPU time
B. System CPU time
C. wasted time
D. execution time


Answer: B. System CPU time

If machine A completes a task in 10 seconds and machine B completes the task in 2 seconds, how many times slower is machine A than machine B?

If machine A completes a task in 10 seconds and machine B completes the task in 2 seconds, how many times slower is machine A than machine B?

A. Five
B. Two and a half
C. Three
D. Four


Answer: A. Five

If machine A completes a task in 10 seconds and machine B completes the task in 2 seconds, how many times faster is machine B than machine A?

If machine A completes a task in 10 seconds and machine B completes the task in 2 seconds, how many times faster is machine B than machine A?

A. Four
B. 400%
C. Two and a half
D. Five


Answer: D. Five

Which of the following indicators are inversely proportional to performance?

Which of the following indicators are inversely proportional to performance?

A. Execution time
B. Clock speed
C. Instructions per second
D. Memory bits transferred per second
E. Throughput
F. Bandwidth
G. Energy or power consumption


Answer:


A. Execution time
G. Energy or power consumption

Sometimes improving bandwidth as opposed to latency is a way of improving performance. Which is an example of improving bandwidth?

Sometimes improving bandwidth as opposed to latency is a way of improving performance. Which is an example of improving bandwidth?

A. Making exams shorter so they can be graded faster
B. More open cashier lanes in the food court
C. Raising the speed limit on I-25 to Denver
D. More streamlined procedures for cashiers in the food court
E. Faster cash registers in the cashier lanes
F. Adding more lanes on I-25 to Denver


Answer:


G. Moving dorms closer to classroom buildings so students can get to class faster
B. More open cashier lanes in the food court
F. Adding more lanes on I-25 to Denver

Performance and execution time are

Performance and execution time are

A. The same thing
B. proportionally related
C. Inversely related
D. exponentially related


Answer: C. Inversely related

Performance is inversely proportional to execution time

Performance is inversely proportional to execution time 

A. T
B. F


Answer: A. T

The total time required for a computer to complete a task, including I/O and operating system overhead is called

The total time required for a computer to complete a task, including I/O and operating system overhead is called

A. Absolute time
B. CPU Time
C. Application time
D. Execution time


Answer: D. Execution time

Quantification of performance can be multi-dimensional. What difficulty does this pose?

Quantification of performance can be multi-dimensional. What difficulty does this pose?

A. Understanding the different dimensions of performance at the same time.
B. Transforming performance to a unidimensional scale so that results can be compared.
C. Knowing whether or not the measurements in different dimensions are equally accurate.
D. Trusting the numbers because statistics can lie.


Answer: B. Transforming performance to a unidimensional scale so that results can be compared.

In addition to cost, what is important in the selection of an off-the-shelf computer for a particular application?

In addition to cost, what is important in the selection of an off-the-shelf computer for a particular application?

A. The speed of the network card.
B. The size of the screen.
C. Limitations in performance.
D. Range of power supply voltages the machine will tolerate


Answer: C. Limitations in performance.

The time it takes a computer to complete a task is an example of

The time it takes a computer to complete a task is an example of

A. Response time
B. Clock frequency
C. Consistency
D. Bandwidth


Answer: A. Response time

A major problem in measuring performance of a computer is

A major problem in measuring performance of a computer is

A. It can be measured several ways
B. Laughing at the English translation of the instruction manual
C. It is impossible to match conditions from run to run
D. Variations in he manufacturing process


Answer: A. It can be measured several ways

Yield is primarily affected by

Yield is primarily affected by

A. Wafer defects
B. feature size
C. N and P doping
D. etching chemistry


Answer: A. Wafer defects

The percentage of good dies on a wafer is called

The percentage of good dies on a wafer is called

A. The success rate
B. Profit
C. The beneficial margin
D. The yield


Answer: D. The yield

The rectangular area on a wafer containing the circuitry for a single chip is a(n)

The rectangular area on a wafer containing the circuitry for a single chip is a(n)

A. imprint
B. module
C. mask
D. die


Answer: D. die

A major difficulty in determining performance is that it

A major difficulty in determining performance is that it

A. No longer relevant in today's computing market
B. Is application dependent
C. Is heavily influenced by marketing
D. Can be measured in different ways
E. Takes a long time to do accurately
F. Can be affected by other components in the computer
G. Is largely independent of the processor itself


Answer:

B. Is application dependent
D. Can be measured in different ways

The chip manufacturing process begins with

The chip manufacturing process begins with

A. Checking the wafer for defects
B. A silicon ingot
C. A large, sausage-shaped piece of silicon
D. Slicing and dicing
E. Slices of silicon about 0.1" thick
F. Photolithography
G. Doping the silicon surface


Answer:

B. A silicon ingot
C. A large, sausage-shaped piece of silicon

Which describe two steps in the chip fabrication process?

Which describe two steps in the chip fabrication process?

A. Slicing and dicing
B. Slipping and shipping
C. Waxing and faxing
D. Testing and resting


Answer: A. Slicing and dicing

The chip fabrication process begins with

The chip fabrication process begins with

A. a package
B. An ingot
C. a wafer
D. a die


Answer: B. An ingot

Silicon is a

Silicon is a

A. Conductor
B. Insulator
C. Semiconductor
D. Transductor


Answer: C. Semiconductor

Current IEEE 802.11 wireless technology allows for data transfer rates of up to

Current IEEE 802.11 wireless technology allows for data transfer rates of up to

A. 100 gigabits per second
B. 1 megabit per second
C. 10 megabits per second
D. 1 gigabit per second
E. 100 megabits per second
D. 1 gigabit per second


Answer: E. 100 megabits per second

Which of the following types of memory is nonvolatile?

Which of the following types of memory is nonvolatile?

A. Flash
B. SRAM
C. DRAM
D. DIMM


Answer: A. Flash

Which memory is non-volatile?

Which memory is non-volatile?

A. Cache
B. Static Random Access Memory (SRAM)
C. Main memory
D. ROM


Answer: D. ROM

A problem with flash memory is that

A problem with flash memory is that

A. The number of writes are limited
B. It is cheaper but slower than magnetic media
C. It cannot be made dense enough (bits/mm^2) to be efficient
D. The bits wear out after too many writes
E. It is more expensive than static RAM
F. It loses its memory when power is turned off
G. The bits are easy to write but difficult to read


Answer:


A. The number of writes are limited
D. The bits wear out after too many writes

Instruction Set Architecture has to do with

Instruction Set Architecture has to do with

A. The layout of circuits on the CPU chip
B. The size and shape of the computer
C. The relationship between the number of cores in a CPU and its ability to exploit parallelism
D. The interface between the lowest level of software and the hardware
E. Die Yield
F. The heat load on the processor when it is running
G. Instructions, register use, memory addressing and I/O operations


Answer:


D. The interface between the lowest level of software and the hardware
G. Instructions, register use, memory addressing and I/O operations

The abstract interface between the hardware and the lowest level of software is called the

The abstract interface between the hardware and the lowest level of software is called the

A. Instruction set architecture
B. Machine design specification
C. Application programming interface
D. Operating system


Answer: A. Instruction set architecture

The iPad processor is the

The iPad processor is the

A. ARM A5
B. Core i7
C. Intel Xeon
D. AMD Barcelona


Answer: A. ARM A5

Which is not a characteristic of Dynamic Random Access Memory (DRAM) (20)

Which is not a characteristic of Dynamic Random Access Memory (DRAM) (20)

A. Refresh cycles are required to retain bit settings (1 or 0)
B. It operates on a slower clock than the CPU
C. It is used for cache
D. It takes very little power
E. It uses one or two transistors per bit
F. It is the most dense in terms of bits per area on a chip
G. It is one of the fastest types of random access memory


Answer:

C. It is used for cache
G. It is one of the fastest types of random access memory