The _________ is a small cache memory associated with the instruction fetch stage of the pipeline.

The _________ is a small cache memory associated with the instruction fetch stage of the pipeline.

A. dynamic branch
B. loop table
C. branch history table
D. flag


Answer: C

A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions in sequence.

A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions in sequence.

A. loop buffer
B. delayed branch
C. multiple stream
D. branch prediction


Answer: A

_______ is a pipeline hazard.

_______ is a pipeline hazard.

A. Control
B. Resource
C. Data
D. All of the above


Answer: D

The ________ determines the opcode and the operand specifiers.

The ________ determines the opcode and the operand specifiers.

A. decode instruction
B. fetch operands
C. calculate operands
D. execute instruction


Answer: A

The _________ contains a word of data to be written to memory or the word most recently read.

The _________ contains a word of data to be written to memory or the word most recently read.

A. MAR
B. PC
C. MBR
D. IR


Answer: C

________ are bits set by the processor hardware as the result of operations.

________ are bits set by the processor hardware as the result of operations.

A. MIPS
B. Condition codes
C. Stacks
D. PSWs


Answer: B

____ is a design principle employed in designing the PDP-10 instruction set.

____ is a design principle employed in designing the PDP-10 instruction set.

a. Orthogonality
b. Completeness
c. Direct addressing
d. All of the above


Answer: All of the above

All instructions in the ARM architecture are __________ bits long and follow a regular format.

All instructions in the ARM architecture are __________ bits long and follow a regular format.

a. 8
b. 16
c. 32
d. 64


Answer: 32

The _________ was designed to provide a powerful and flexible instruction set within the constraints of a 16-bit minicomputer.

The _________ was designed to provide a powerful and flexible instruction set within the constraints of a 16-bit minicomputer.

a. PDP-1
b. PDP-8
c. PDP-11
d. PDP-10


Answer: PDP-11

_______ is a principle by which two variables are independent of each other.

_______ is a principle by which two variables are independent of each other.

a. Opcode
b. Orthogonality
c. Completeness
d. Autoindexing


Answer: Orthogonality

The only form of addressing for branch instructions is _________ addressing.

The only form of addressing for branch instructions is _________ addressing.

a. register
b. relative
c. base
d. immediate


Answer: immediate

_______ has the advantage of flexibility, but the disadvantage of complexity.

_______ has the advantage of flexibility, but the disadvantage of complexity.

a. Stack addressing
b. Displacement addressing
c. Direct addressing
d. Register addressing


Answer: Displacement addressing

_____ has the advantage of large address space, however it has the disadvantage of multiple memory references.

_____ has the advantage of large address space, however it has the disadvantage of multiple memory references.

a. Indirect addressing
b. Direct addressing
c. Immediate addressing
d. Stack addressing


Answer: Indirect addressing

The advantage of __________ is that no memory reference other than the instruction fetch is required to obtain the operand.

The advantage of __________ is that no memory reference other than the instruction fetch is required to obtain the operand.

a. direct addressing
b. immediate addressing
c. register addressing
d. stack addressing


Answer: immediate addressing

A branch instruction in which the branch is always taken is _________.

A branch instruction in which the branch is always taken is _________.

a. conditional branch
b. unconditional branch
c. jump
d. bi-endian


Answer: unconditional branch

The entire set of parameters, including return address, which is stored for a procedure invocation is referred to as a _________.

The entire set of parameters, including return address, which is stored for a procedure invocation is referred to as a _________.

a. branch
b. stack frame
c. pop
d. push


Answer: stack frame

Which of the following is a true statement?

Which of the following is a true statement?

a. a procedure can be called from more than one location
b. a procedure call can appear in a procedure
c. each procedure call is matched by a return in the called program
d. all of the above


Answer: all of the above

The most fundamental type of machine instruction is the _________ instruction.

The most fundamental type of machine instruction is the _________ instruction.

a. conversion
b. data transfer
c. arithmetic
d. logical


Answer: data transfer

_______ instructions provide computational capabilities for processing number data.

_______ instructions provide computational capabilities for processing number data.

a. Boolean
b. Logic
c. Memory
d. Arithmetic


Answer: Arithmetic

The _________ table provides the value of the next output when the inputs and the present output are known, which is exactly the information needed to design the counter or any sequential circuit.

The _________ table provides the value of the next output when the inputs and the present output are known, which is exactly the information needed to design the counter or any sequential circuit.

a. excitation
b. Kenough
c. J-K flip-flop
d. FPGA


Answer: excitation

Counters can be designated as _________.

Counters can be designated as _________.

a. asynchronous
b. synchronous
c. both asynchronous and synchronous
d. neither asynchronous or synchronous


Answer: both asynchronous and synchronous

A _________ accepts and/or transfers information serially.

A _________ accepts and/or transfers information serially.

a. S-R latch
b. shift register
c. FPGA
d. parallel register



Answer: shift register

The ________ exists in one of two states and, in the absence of input, remains in that state.

The ________ exists in one of two states and, in the absence of input, remains in that state.

a. assert
b. complex PLD
c. decoder
d. flip-flop


Answer: flip-flop

For more than four variables an alternative approach is a tabular technique referred to as the _________ method.

For more than four variables an alternative approach is a tabular technique referred to as the _________ method.

a. DeMorgan
b. Quine-McCluskey
c. Karnaugh map
d. Boole-Shannon


Answer: Quine-McCluskey

Which of the following is a functionally complete set?

Which of the following is a functionally complete set?

a. AND, NOT
b. NOR
c. AND, OR, NOT
d. all of the above


Answer: all of the above

A _______ is an electronic circuit that produces an output signal that is a simple Boolean operation on its input signals.

A _______ is an electronic circuit that produces an output signal that is a simple Boolean operation on its input signals.

a. gate
b. decoder
c. counter
d. flip-flop


Answer: gate

The unary operation _________ inverts the value of its operand.

The unary operation _________ inverts the value of its operand.

a. OR
b. NOT
c. NAND
d. XOR


Answer: NOT

The operation _________ yields true if either or both of its operands are true.

The operation _________ yields true if either or both of its operands are true.

a. NOT
b. AND
c. NAND
d. OR


Answer: OR

Binary 0101 is hexadecimal _________.

Binary 0101 is hexadecimal _________.

a. 0
b. 5
c. A
d. 10


Answer: 5

Another term for "base" is __________.

Another term for "base" is __________.

a. radix
b. integer
c. position
d. digit


Answer: radix

Decimal "10" is __________ in binary.

Decimal "10" is __________ in binary.

a. 1000
b. 0010
c. 1010
d. 0001


Answer: 1010

Hexadecimal has a base of _________.

Hexadecimal has a base of _________.

a. 2
b. 8
c. 10
d. 16


Answer: 16

Numbers in the binary system are represented to the _________.

Numbers in the binary system are represented to the _________.

a. base 0
b. base 1
c. base 2
d. base 10


Answer: base 2

In the number 3109, the 3 is referred to as the _________.

In the number 3109, the 3 is referred to as the _________.

a. most significant digit
b. least significant digit
c. radix
d. base


Answer: most significant digit

Which of the following is correct?

Which of the following is correct?

a. 25 = (2 x 102) + (5 x 101)
b. 289 = (2 x 103) + (8 x 101) + (9 x 100)
c. 7523 = (7 x 103) + (5 x 102) + (2 x 101) + (3 x 100)
d. 0.628 = (6 x 10-3) + (2 x 10-2) + (8 x 10-1)


Answer: 7523 = (7 x 103) + (5 x 102) + (2 x 101) + (3 x 100)

Which digit represents "hundreds" in the number 8732?

Which digit represents "hundreds" in the number 8732?

a. 8
b. 7
c. 3
d. 2

Answer: 7

The OS maintains a __________ for each process that shows the frame location for each page of the process.

The OS maintains a __________ for each process that shows the frame location for each page of the process.

a. kernel
b. page table
c. TLB
d. logical address


Answer: page table

A _________ is a collection of memory regions.

A _________ is a collection of memory regions.

a. APX
b. nucleus
c. domain
d. page table


Answer: domain

The _________ scheduler determines which programs are admitted to the system for processing.

The _________ scheduler determines which programs are admitted to the system for processing.

a. long-term
b. medium-term
c. short-term
d. I/O


Answer: long-term

A _________ is a special type of programming language used to provide instructions to the monitor.

A _________ is a special type of programming language used to provide instructions to the monitor.

a. job control language
b. multiprogram
c. kernel
d. utility


Answer: job control language

A _________ system works only one program at a time.

A _________ system works only one program at a time.

a. batch
b. uniprogramming
c. kernel
d. privileged instruction


Answer: uniprogramming

The ________ gives a program access to the hardware resources and services available in a system through the user instruction set architecture supplemented with high-level language library calls.

The ________ gives a program access to the hardware resources and services available in a system through the user instruction set architecture supplemented with high-level language library calls.

a. JCL
b. ISA
c. ABI
d. API


Answer: API

The _________ defines the repertoire of machine language instructions that a computer can follow.

The _________ defines the repertoire of machine language instructions that a computer can follow.

a. ABI
b. API
c. HLL
d. ISA


Answer: ISA

Facilities and services provided by the OS that assist the programmer in creating programs are in the form of _________ programs that are not actually part of the OS but are accessible through the OS.

Facilities and services provided by the OS that assist the programmer in creating programs are in the form of _________ programs that are not actually part of the OS but are accessible through the OS.

a. utility
b. multitasking
c. JCL
d. logical address


Answer: utility

A ________ connects InfiniBand subnets, or connects an InfiniBand switch to a network such as a local area network, wide area network, or storage area network.

A ________ connects InfiniBand subnets, or connects an InfiniBand switch to a network such as a local area network, wide area network, or storage area network.

a. memory controller
b. TCA
c. HCA
d. router


Answer: router

______ is a digital display interface standard now widely adopted for computer monitors, laptop displays, and other graphics and video interfaces.

______ is a digital display interface standard now widely adopted for computer monitors, laptop displays, and other graphics and video interfaces.

a. DisplayPort
b. PCI Express
c. Thunderbolt
d. InfiniBand


Answer: DisplayPort

The 8237 DMA is known as a _________ DMA controller.

The 8237 DMA is known as a _________ DMA controller.

a. command
b. cycle stealing
c. interrupt
d. fly-by

Answer: fly-by

_____ is when the DMA module must force the processor to suspend operation temporarily.

_____ is when the DMA module must force the processor to suspend operation temporarily.

a. Interrupt
b. Thunderbolt
c. Cycle stealing
d. Lock down


Answer: Cycle stealing

The _________ command causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral.

The _________ command causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral.

a. control
b. test
c. read
d. write


Answer: write

An I/O module that is quite primitive and requires detailed control is usually referred to as an _________.

An I/O module that is quite primitive and requires detailed control is usually referred to as an _________.

a. I/O command
b. I/O controller
c. I/O channel
d. I/O processor


Answer: I/O controller

An I/O module that takes on most of the detailed processing burden, presenting a high-level interface to the processor, is usually referred to as an _________.

An I/O module that takes on most of the detailed processing burden, presenting a high-level interface to the processor, is usually referred to as an _________.

a. I/O channel
b. I/O command
c. I/O controller
d. device controller


Answer: I/O channel

The most common means of computer/user interaction is a __________.

The most common means of computer/user interaction is a __________.

a. keyboard/monitor
b. mouse/printer
c. modem/printer
d. monitor/printer


Answer: keyboard/monitor

The _________ contains logic for performing a communication function between the peripheral and the bus.

The _________ contains logic for performing a communication function between the peripheral and the bus.

a. I/O channel
b. I/O module
c. I/O processor
d. I/O command


Answer: I/O module

_____ is when the disk rotates more slowly for accesses near the outer edge than for those near the center.

_____ is when the disk rotates more slowly for accesses near the outer edge than for those near the center.

a. Constant angular velocity (CAV)
b. Magnetoresistive
c. Constant linear velocity (CLV)
d. Seek time


Answer: Constant linear velocity (CLV)

A _________ is a high-definition video disk that can store 25 Gbytes on a single layer on a single side.

A _________ is a high-definition video disk that can store 25 Gbytes on a single layer on a single side.

a. DVD
b. DVD-R
c. DVD-RW
d. Blu-ray DVD


Answer: Blu-ray DVD

________ is the standardized scheme for multiple-disk database design.

________ is the standardized scheme for multiple-disk database design.

a. RAID
b. CAV
c. CLV
d. SSD


Answer: RAID

The sum of the seek time and the rotational delay equals the _________, which is the time it takes to get into position to read or write.

The sum of the seek time and the rotational delay equals the _________, which is the time it takes to get into position to read or write.

a. access time
b. gap time
c. transfer time
d. constant angular velocity


Answer: access time

When the magnetizable coating is applied to both sides of the platter the disk is then referred to as _________.

When the magnetizable coating is applied to both sides of the platter the disk is then referred to as _________.

a. multiple sided
b. substrate
c. double sided
d. all of the above


Answer: double sided

A __________ disk is permanently mounted in the disk drive, such as the hard disk in a personal computer.

A __________ disk is permanently mounted in the disk drive, such as the hard disk in a personal computer.

a. nonremovable
b. movable-head
c. double sided
d. removable


Answer: nonremovable

The disadvantage of _________ is that the amount of data that can be stored on the long outer tracks is only the same as what can be stored on the short inner tracks.

The disadvantage of _________ is that the amount of data that can be stored on the long outer tracks is only the same as what can be stored on the short inner tracks.

a. SSD
b. CAV
c. ROM
d. CLV


Answer: CAV

Scanning information at the same rate by rotating the disk at a fixed speed is known as the _________.

Scanning information at the same rate by rotating the disk at a fixed speed is known as the _________.

a. constant angular velocity
b. magnetoresistive
c. rotational delay
d. constant linear velocity


Answer: constant angular velocity

Data are transferred to and from the disk in __________.

Data are transferred to and from the disk in __________.

a. tracks
b. gaps
c. sectors
d. pits


Answer: sectors

Adjacent tracks are separated by _________.

Adjacent tracks are separated by _________.

a. sectors
b. gaps
c. pits
d. heads


Answer: gaps

Greater ability to withstand shock and damage, improvement in the uniformity of the magnet film surface to increase disk reliability, and a significant reduction in overall surface defects to help reduce read-write errors, are all benefits of ___________.

Greater ability to withstand shock and damage, improvement in the uniformity of the magnet film surface to increase disk reliability, and a significant reduction in overall surface defects to help reduce read-write errors, are all benefits of ___________.

a. magnetic read and write mechanisms
b. platters
c. the glass substrate
d. a solid state drive


Answer: the glass substrate

The ________ enables the RAM chip to preposition bits to be placed on the data bus as rapidly as possible.

The ________ enables the RAM chip to preposition bits to be placed on the data bus as rapidly as possible.

a. flash memory
b. Hamming code
c. RamBus
d. buffer


Answer: buffer

_________ increases the data transfer rate by increasing the operational frequency of the RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits per chip.

_________ increases the data transfer rate by increasing the operational frequency of the RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits per chip.

a. DDR2
b. RDRAM
c. CDRAM
d. DDR3


Answer: DDR2

The _________ exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states.

The _________ exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states.

a. DDR-DRAM
b. SDRAM
c. CDRAM
d. none of the above


Answer: SDRAM

________ can be caused by power supply problems or alpha particles.

________ can be caused by power supply problems or alpha particles.

a. Soft errors
b. AGT errors
c. Hard errors
d. SEC errors


Answer: Soft errors

With _________ the microchip is organized so that a section of memory cells are erased in a single action.

With _________ the microchip is organized so that a section of memory cells are erased in a single action.

a. flash memory
b. SDRAM
c. DRAM
d. EEPROM

Answer: flash memory

A __________ contains a permanent pattern of data that cannot be changed, is nonvolatile, and cannot have new data written into it.

A __________ contains a permanent pattern of data that cannot be changed, is nonvolatile, and cannot have new data written into it.

a. RAM
b. SRAM
c. ROM
d. flash memory


Answer: ROM

Which of the following memory types are nonvolatile?

Which of the following memory types are nonvolatile?

a. erasable PROM
b. programmable ROM
c. flash memory
d. all of the above


Answer: all of the above

One distinguishing characteristic of memory that is designated as _________ is that it is possible to both to read data from the memory and to write new data into the memory easily and rapidly.

One distinguishing characteristic of memory that is designated as _________ is that it is possible to both to read data from the memory and to write new data into the memory easily and rapidly.

a. RAM
b. ROM
c. EPROM
d. EEPROM


Answer: RAM

Which properties do all semiconductor memory cells share?

Which properties do all semiconductor memory cells share?

a. they exhibit two stable states which can be used to represent binary 1 and 0
b. they are capable of being written into to set the state
c. they are capable of being read to sense the state
d. all of the above


Answer: all of the above

In reference to access time to a two-level memory, a _________ occurs if an accessed word is not found in the faster memory.

In reference to access time to a two-level memory, a _________ occurs if an accessed word is not found in the faster memory.

a. miss
b. hit
c. line
d. tag


Answer: miss

The key advantage of the __________ design is that it eliminates contention for the cache between the instruction fetch/decode unit and the execution unit.

The key advantage of the __________ design is that it eliminates contention for the cache between the instruction fetch/decode unit and the execution unit.

a. logical cache
b. split cache
c. unified cache
d. physical cache


Answer: split cache

When using the __________ technique all write operations made to main memory are made to the cache as well.

When using the __________ technique all write operations made to main memory are made to the cache as well.

a. write back
b. LRU
c. write through
d. unified cache


Answer: write through

________ is the simplest mapping technique and maps each block of main memory into only one possible cache line.

________ is the simplest mapping technique and maps each block of main memory into only one possible cache line.

a. Direct mapping
b. Associative mapping
c. Set associative mapping
d. None of the above


Answer: Direct mapping

A line includes a _________ that identifies which particular block is currently being stored.

A line includes a _________ that identifies which particular block is currently being stored.

a. cache
b. hit
c. tag
d. locality


Answer: tag

The ________ consists of the access time plus any additional time required before a second access can commence.

The ________ consists of the access time plus any additional time required before a second access can commence.

a. latency
b. memory cycle time
c. direct access
d. transfer rate


Answer: memory cycle time

For random-access memory, __________ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use.

For random-access memory, __________ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use.

a. memory cycle time
b. direct access
c. transfer rate
d. access time


Answer: access time

An individual blocks or records have a unique address based on physical location with __________.

An individual blocks or records have a unique address based on physical location with __________.

a. associative
b. physical access
c. direct access
d. sequential access


Answer: direct access

"Memory is organized into records and access must be made in a specific linear sequence" is a description of __________.

"Memory is organized into records and access must be made in a specific linear sequence" is a description of __________.

a. sequential access
b. direct access
c. random access
d. associative


Answer: sequential access

For internal memory, the __________ is equal to the number of electrical lines into and out of the memory module.

For internal memory, the __________ is equal to the number of electrical lines into and out of the memory module.

a. access time
b. unit of transfer
c. capacity
d. memory ratio


Answer: unit of transfer

The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer.

The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer.

a. transaction layer
b. root layer
c. configuration layer
d. transport layer


Answer: transaction layer

A sequence of codes or instructions is called __________.

A sequence of codes or instructions is called __________.

a. software
b. memory
c. an interconnect
d. a register


Answer: software

The QPI _________ layer is used to determine the course that a packet will traverse across the available system interconnects.

The QPI _________ layer is used to determine the course that a packet will traverse across the available system interconnects.

a. link
b. protocol
c. routing
d. physical


Answer: routing

A __________ is the high-level set of rules for exchanging packets of data between devices.

A __________ is the high-level set of rules for exchanging packets of data between devices.

a. bus
b. protocol
c. packet
d. QPI


Answer: protocol

A(n) _________ is generated by some condition that occurs as a result of an instruction execution.

A(n) _________ is generated by some condition that occurs as a result of an instruction execution.

a. timer interrupt
b. I/O interrupt
c. program interrupt
d. hardware failure interrupt


Answer: program interrupt

Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies, Princeton.

Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies, Princeton.

a. John Maulchy
b. John von Neumann
c. Herman Hollerith
d. John Eckert


Answer: John von Neumann

The processing required for a single instruction is called a(n) __________ cycle.

The processing required for a single instruction is called a(n) __________ cycle.

a. execute
b. fetch
c. instruction
d. packet


Answer: instruction

The data lines provide a path for moving data among system modules and are collectively called the _________.

The data lines provide a path for moving data among system modules and are collectively called the _________.

a. control bus
b. address bus
c. data bus
d. system bus


Answer: data bus

The interconnection structure must support which transfer?

The interconnection structure must support which transfer?

a. memory to processor
b. processor to memory
c. I/O to or from memory
d. all of the above


Answer: all of the above

The TL supports which of the following address spaces?

The TL supports which of the following address spaces?

a. memory
b. I/O
c. message
d. all of the above


Answer: all of the above

The von Neumann architecture is based on which concept?

The von Neumann architecture is based on which concept?

a. data and instructions are stored in a single read-write memory
b. the contents of this memory are addressable by location
c. execution occurs in a sequential fashion
d. all of the above


Answer: all of the above

ARM processors are designed to meet the needs of _________.

ARM processors are designed to meet the needs of _________.

a. embedded real-time systems
b. application platforms
c. secure applications
d. all of the above

Answer: all of the above

With the __________, Intel introduced the use of superscalar techniques that allow multiple instructions to execute in parallel.

With the __________, Intel introduced the use of superscalar techniques that allow multiple instructions to execute in parallel.

a. Core
b. 8080
c. 80486
d. Pentium


Answer: Pentium

The use of multiple processors on the same chip is referred to as __________ and provides the potential to increase performance without increasing the clock rate.

The use of multiple processors on the same chip is referred to as __________ and provides the potential to increase performance without increasing the clock rate.

a. multicore
b. GPU
c. data channels
d. MPC


Answer: multicore

During the _________ the opcode of the next instruction is loaded into the IR and the address portion is loaded into the MAR.

During the _________ the opcode of the next instruction is loaded into the IR and the address portion is loaded into the MAR.

a. execute cycle
b. fetch cycle
c. instruction cycle
d. clock cycle


Answer: fetch cycle

The memory of the IAS consists of 1000 storage locations called __________.

The memory of the IAS consists of 1000 storage locations called __________.

a. opcodes
b. wafers
c. VLSIs
d. words


Answer: words

The __________ interprets the instructions in memory and causes them to be executed.

The __________ interprets the instructions in memory and causes them to be executed.

a. main memory
b. control unit
c. I/O
d. arithmetic and logic unit


Answer: control unit

The ENIAC used __________.

The ENIAC used __________.

a. vacuum tubes
b. integrated circuits
c. IAS


Answer: vacuum tubes

The Electronic Numerical Integrator and Computer project was a response to U.S. needs during _________.

The Electronic Numerical Integrator and Computer project was a response to U.S. needs during _________.

a. the Civil War
b. the French-American War
c. World War I
d. World War II


Answer: World War II

The _________ stores data.

The _________ stores data.

a. system bus
b. I/O
c. main memory
d. control unit


Answer: main memory

The __________ moves data between the computer and its external environment.

The __________ moves data between the computer and its external environment.

a. data transport
b. I/O
c. register
d. CPU interconnection


Answer: I/O

A common example of system interconnection is by means of a __________.

A common example of system interconnection is by means of a __________.

a. register
b. system bus
c. data transport
d. control device


Answer: system bus

The _________ was the world's first general-purpose electronic digital computer.

The _________ was the world's first general-purpose electronic digital computer.

a. UNIVAC
b. MARK IV
c. ENIAC
d. Hollerith's Counting Machine


Answer: ENIAC

________ attributes include hardware details transparent to the programmer.

________ attributes include hardware details transparent to the programmer.

a. Interface
b. Organizational
c. Memory
d. Architectural


Answer: Organizational

It is a(n) _________ design issue whether a computer will have a multiply instruction.

It is a(n) _________ design issue whether a computer will have a multiply instruction.

a. architectural
b. memory
c. elementary
d. organizational


Answer: architectural

It is a(n) _________ issue whether the multiply instruction will be implemented by a special multiply unit or by a mechanism that makes repeated use of the add unit of the system.

It is a(n) _________ issue whether the multiply instruction will be implemented by a special multiply unit or by a mechanism that makes repeated use of the add unit of the system.

a. architectural
b. memory
c. mechanical
d. organizational


Answer: organizational

A __________ system is a set of interrelated subsystems.

A __________ system is a set of interrelated subsystems.

a. secondary
b. hierarchical
c. complex
d. functional


Answer: hierarchical

When data are moved over longer distances, to or from a remote device, the process is known as __________.

When data are moved over longer distances, to or from a remote device, the process is known as __________.

a. data communications
b. registering
c. structuring
d. data transport


Answer: data communications

Computer technology is changing at a __________ pace.

Computer technology is changing at a __________ pace.

a. slow
b. slow to medium
c. rapid
d. non-existent


Answer: rapid

Computer _________ refers to those attributes that have a direct impact on the logical execution of a program.

Computer _________ refers to those attributes that have a direct impact on the logical execution of a program.

a. organization
b. specifics
c. design
d. architecture


Answer: architecture

The MIPS R4000 uses ________ bits for all internal and external data paths and for addresses, registers, and the ALU.

The MIPS R4000 uses ________ bits for all internal and external data paths and for addresses, registers, and the ALU.

a. 16
b. 32
c. 64
d. 128


Answer: 64

SPARC refers to an architecture defined by ________.

SPARC refers to an architecture defined by ________.

a. Microsoft
b. Apple
c. Sun Microsystems
d. IBM


Answer: Sun Microsystems

The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage.

The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage.

a. write back
b. tag check
c. data cache
d. instruction execute


Answer: write back

The first commercial RISC product was _________.

The first commercial RISC product was _________.

a. SPARC
b. CISC
c. VAX
d. the Pyramid


Answer: the Pyramid

Which stage is required for load and store operations?

Which stage is required for load and store operations?

a. I
b. E
c. D
d. all of the above


Answer: all of the above

A ________ instruction can be used to account for data and branch delays.

A ________ instruction can be used to account for data and branch delays.

a. SUB
b. NOOP
c. JUMP
d. all of the above


Answer: NOOP

The instruction location immediately following the delayed branch is referred to as the ________.

The instruction location immediately following the delayed branch is referred to as the ________.

a. delay load
b. delay file
c. delay slot
d. delay register


Answer: delay slot

_________ determines the control and pipeline organization.

_________ determines the control and pipeline organization.

a. Calculation
b. Execution sequencing
c. Operations performed
d. Operands used


Answer: Execution sequencing

______ registers may be used only to hold data and cannot be employed in the calculation of an operand address.

______ registers may be used only to hold data and cannot be employed in the calculation of an operand address.

A. General purpose
B. Data
C. Address
D. Condition code


Answer: B

_____ is used for debugging.

_____ is used for debugging.

A. Direction flag
B. Alignment check
C. Trap flag
D. Identification flag


Answer: C

For the _________ mode, the operand is included in the instruction.

For the _________ mode, the operand is included in the instruction.

a. immediate
b. base
c. register
d. displacement


Answer: immediate

Which of the following interrelated factors go into determining the use of the addressing bits?

Which of the following interrelated factors go into determining the use of the addressing bits?

a. number of operands
b. number of register sets
c. address range
d. all of the above


Answer: all of the above

The __________ byte consists of three fields: the Scale field, the Index field and the Base field.

The __________ byte consists of three fields: the Scale field, the Index field and the Base field.

a. SIB
b. VAX
c. PDP-11
d. ModR/M


Answer: SIB

_____ are a set of storage locations.

_____ are a set of storage locations.

A. Processors
B. PSWs
C. Registers
D. Control units


Answer: C

For _________, the address field references a main memory address and the referenced register contains a positive displacement from that address.

For _________, the address field references a main memory address and the referenced register contains a positive displacement from that address.

a. indexing
b. base-register addressing
c. relative addressing
d. all of the above


Answer: indexing

Indexing performed after the indirection is __________.

Indexing performed after the indirection is __________.

a. relative addressing
b. autoindexing
c. postindexing
d. preindexing



Answer: postindexing

Which data type is defined in MMX?

Which data type is defined in MMX?

a. packed byte
b. packed word
c. packed doubleword
d. all of the above


Answer: all of the above

The principal advantage of ___________ addressing is that it is a very simple form of addressing.

The principal advantage of ___________ addressing is that it is a very simple form of addressing.

a. displacement
b. register
c. stack
d. direct


Answer: direct

The advantages of _________ addressing are that only a small address field is needed in the instruction and no time-consuming memory references are required.

The advantages of _________ addressing are that only a small address field is needed in the instruction and no time-consuming memory references are required.

a. direct
b. indirect
c. register
d. displacement


Answer: register

_______ instructions are needed to transfer programs and data into memory and the results of computations back out to the user.

_______ instructions are needed to transfer programs and data into memory and the results of computations back out to the user.

a. I/O
b. Transfer
c. Control
d. Branch


Answer: I/O

The x86 data type that is a signed binary value contained in a byte, word, or doubleword, using twos complement representation is _________.

The x86 data type that is a signed binary value contained in a byte, word, or doubleword, using twos complement representation is _________.

a. general
b. ordinal
c. integer
d. packed BCD


Answer: integer

The _________ instruction includes an implied address.

The _________ instruction includes an implied address.

a. skip
b. rotate
c. stack
d. push


Answer: skip

Which ARM operation category includes logical instructions (AND, OR, XOR), add and subtract instructions, and test and compare instructions?

Which ARM operation category includes logical instructions (AND, OR, XOR), add and subtract instructions, and test and compare instructions?

a. data-processing instructions
b. branch instructions
c. load and store instructions
d. extend instructions


Answer: data-processing instructions

In the ARM architecture only _________ instructions access memory locations.

In the ARM architecture only _________ instructions access memory locations.

a. data processing
b. status register access
c. load and store
d. branch


Answer: load and store

A(n) _________ expresses operations in a concise algebraic form using variables.

A(n) _________ expresses operations in a concise algebraic form using variables.

a. opcode
b. high-level language
c. machine language
d. register


Answer: high-level language

There must be ________ instructions for moving data between memory and the registers.

There must be ________ instructions for moving data between memory and the registers.

a. branch
b. logic
c. memory
d. I/O


Answer: memory

______ instructions operate on the bits of a word as bits rather than as numbers, providing capabilities for processing any other type of data the user may wish to employ.

______ instructions operate on the bits of a word as bits rather than as numbers, providing capabilities for processing any other type of data the user may wish to employ.

a. Logic
b. Arithmetic
c. Memory
d. Test


Answer: Logic

______ are used in digital circuits to control signal and data routing.

______ are used in digital circuits to control signal and data routing.

a. Multiplexers
b. Program counters
c. Flip-flops
d. Gates


Answer: Multiplexers

_______ is implemented with combinational circuits.

_______ is implemented with combinational circuits.

a. Nano memory
b. Random access memory
c. Read only memory
d. No memory


Answer: Read only memory

The ________ flip-flop has two inputs and all possible combinations of input values are valid.

The ________ flip-flop has two inputs and all possible combinations of input values are valid.

a. J-K
b. D
c. S-R
d. clocked S-R


Answer: J-K

CPUs make use of _________ counters, in which all of the flip-flops of the counter change at the same time.

CPUs make use of _________ counters, in which all of the flip-flops of the counter change at the same time.

a. synchronous
b. asynchronous
c. clocked S-R
d. timed ripple


Answer: synchronous

The ________ specifies the operation to be performed.

The ________ specifies the operation to be performed.

a. source operand reference
b. opcode
c. next instruction reference
d. processor register


Answer: opcode

Four bits is called a _________.

Four bits is called a _________.

a. radix point
b. byte
c. nibble
d. binary digit


Answer: nibble

In the number 472.156 the 2 is the _________.

In the number 472.156 the 2 is the _________.

a. most significant digit
b. radix point
c. least significant digit
d. none of the above


Answer: none of the above

The operand ________ yields true if and only if both of its operands are true.

The operand ________ yields true if and only if both of its operands are true.

a. XOR
b. OR
c. AND
d. NOT


Answer: AND

Decimal "10" is _________ in hexadecimal.

Decimal "10" is _________ in hexadecimal.

a. 1
b. A
c. 0
d. FF


Answer: A

With _________ the virtual address is the same as the physical address.

With _________ the virtual address is the same as the physical address.

a. unsegmented unpaged memory
b. unsegmented paged memory
c. segmented unpaged memory
d. segmented paged memory


Answer: unsegmented unpaged memory

The decimal system has a base of _________.

The decimal system has a base of _________.

a. 0
b. 10
c. 100
d. 1000


Answer: 10

In the number 3109, the 9 is referred to as the _________.

In the number 3109, the 9 is referred to as the _________.

a. most significant digit
b. least significant digit
c. radix
d. base


Answer: least significant digit

The binary string 110111100001 is equivalent to __________.

The binary string 110111100001 is equivalent to __________.

a. DE116
b. C7816
c. FF6416
d. B8F16


Answer: DE116

The _________ system uses only the numbers 0 and 1.

The _________ system uses only the numbers 0 and 1.

a. positional
b. binary
c. hexadecimal
d. decimal


Answer: binary

The _________ defines the system call interface to the operating system and the hardware resources and services available in a system through the user instruction set architecture.

The _________ defines the system call interface to the operating system and the hardware resources and services available in a system through the user instruction set architecture.

a. HLL
b. API
c. ABI
d. ISA


Answer: ABI

The ________ scheduler is also known as the dispatcher.

The ________ scheduler is also known as the dispatcher.

a. long-term
b. medium-term
c. short-term
d. I/O


Answer: short-term

A _________ is an actual location in main memory.

A _________ is an actual location in main memory.

a. logical address
b. partition address
c. base address
d. physical address


Answer: physical address

_______ is when the processor spends most of its time swapping pages rather than executing instructions.

_______ is when the processor spends most of its time swapping pages rather than executing instructions.

a. Swapping
b. Thrashing
c. Paging
d. Multitasking


Answer: Thrashing

Virtual memory schemes make use of a special cache called a ________ for page table entries.

Virtual memory schemes make use of a special cache called a ________ for page table entries.

a. TLB
b. HLL
c. VMC
d. SPB


Answer: TLB

The ________ command is used to activate a peripheral and tell it what to do.

The ________ command is used to activate a peripheral and tell it what to do.

a. control
b. test
c. read
d. write


Answer: control

The Thunderbolt protocol _________ layer is responsible for link maintenance including hot-plug detection and data encoding to provide highly efficient data transfer.

The Thunderbolt protocol _________ layer is responsible for link maintenance including hot-plug detection and data encoding to provide highly efficient data transfer.

a. cable
b. application
c. common transport
d. physical


Answer: physical

A ________ is used to connect storage systems, routers, and other peripheral devices to an InfiniBand switch.

A ________ is used to connect storage systems, routers, and other peripheral devices to an InfiniBand switch.

a. target channel adapter
b. InfiniBand switch
c. host channel adapter
d. subnet


Answer: target channel adapter

The __________ is a program that controls the execution of application programs and acts as an interface between applications and the computer hardware.

The __________ is a program that controls the execution of application programs and acts as an interface between applications and the computer hardware.

a. job control language
b. operating system
c. batch system
d. nucleus


Answer: operating system

Theoretically, a DDR module can transfer data at a clock rate in the range of __________ MHz.

Theoretically, a DDR module can transfer data at a clock rate in the range of __________ MHz.

a. 200 to 600
b. 400 to 1066
c. 600 to 1400
d. 800 to 1600


Answer: 200 to 600

A DDR3 module transfers data at a clock rate of __________ MHz.A DDR3 module transfers data at a clock rate of __________ MHz.

A DDR3 module transfers data at a clock rate of __________ MHz.

a. 600 to 1200
b. 800 to 1600
c. 1000 to 2000
d. 1500 to 3000


Answer: 800 to 1600

In most contemporary systems fixed-length sectors are used, with _________ bytes being the nearly universal sector size.

In most contemporary systems fixed-length sectors are used, with _________ bytes being the nearly universal sector size.

a. 64
b. 128
c. 256
d. 512


Answer: 512

The set of all the tracks in the same relative position on the platter is referred to as a _________.

The set of all the tracks in the same relative position on the platter is referred to as a _________.

a. floppy disk
b. single-sided disk
c. sector
d. cylinder


Answer: cylinder

The I/O function includes a _________ requirement to coordinate the flow of traffic between internal resources and external devices.

The I/O function includes a _________ requirement to coordinate the flow of traffic between internal resources and external devices.

a. cycle
b. status reporting
c. control and timing
d. data


Answer: control and timing

______ can send data to the processor twice per clock cycle.

______ can send data to the processor twice per clock cycle.

a. CDRAM
b. SDRAM
c. DDR-DRAM
d. RDRAM


Answer: DDR-DRAM

The Pentium 4 _________ component executes micro-operations, fetching the required data from the L1 data cache and temporarily storing results in registers.

The Pentium 4 _________ component executes micro-operations, fetching the required data from the L1 data cache and temporarily storing results in registers.

a. fetch/decode unit
b. out-of-order execution logic
c. execution unit
d. memory subsystem


Answer: execution unit

A logical cache stores data using __________.

A logical cache stores data using __________.

a. physical addresses
b. virtual addresses
c. random addresses
d. none of the above


Answer: virtual addresses

In a _________, binary values are stored using traditional flip-flop logic-gate configurations.

In a _________, binary values are stored using traditional flip-flop logic-gate configurations.

a. ROM
b. SRAM
c. DRAM
d. RAM


Answer: SRAM

_______ can be caused by harsh environmental abuse, manufacturing defects, and wear.

_______ can be caused by harsh environmental abuse, manufacturing defects, and wear.

a. SEC errors
b. Hard errors
c. Syndrome errors
d. Soft errors


Answer: Hard errors

Each data path consists of a pair of wires (referred to as a __________) that transmits data one bit at a time.

Each data path consists of a pair of wires (referred to as a __________) that transmits data one bit at a time.

a. lane
b. path
c. line
d. bus


Answer: lane

A bus that connects major computer components (processor, memory, I/O) is called a __________.

A bus that connects major computer components (processor, memory, I/O) is called a __________.

a. system bus
b. address bus
c. data bus
d. control bus


Answer: system bus

_______ refers to whether memory is internal or external to the computer.

_______ refers to whether memory is internal or external to the computer.

a. Location
b. Access
c. Hierarchy
d. Tag


Answer: Location

Internal memory capacity is typically expressed in terms of _________.

Internal memory capacity is typically expressed in terms of _________.

a. hertz
b. nanos
c. bytes
d. LOR


Answer: bytes

A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred to as a _________.

A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred to as a _________.

a. disk cache
b. latency
c. virtual address
d. miss


Answer: disk cache

A(n) _________ is generated by a failure such as power failure or memory parity error.

A(n) _________ is generated by a failure such as power failure or memory parity error.

a. I/O interrupt
b. hardware failure interrupt
c. timer interrupt
d. program interrupt


Answer: hardware failure interrupt

One increment, or pulse, of the system clock is referred to as a _________.

One increment, or pulse, of the system clock is referred to as a _________.

a. clock tick
b. cycle time
c. clock rate
d. cycle speed


Answer: A

The __________ measures the ability of a computer to complete a single task.

The __________ measures the ability of a computer to complete a single task.

a. clock speed
b. speed metric
c. execute cycle
d. cycle time


Answer: B

Second generation computers used __________.

Second generation computers used __________.

a. integrated circuits
b. Transistors
c. vacuum tubes
d. large-scale integration


Answer: B

The __________ defines the third generation of computers.

The __________ defines the third generation of computers.

a. integrated circuit
b. vacuum tube
c. transistor
d. VLSI

Answer: A

The __________ performs the computer's data processing functions.

The __________ performs the computer's data processing functions.

a. Register
b. CPU interconnection
c. ALU
d. system bus


Answer: C

The ENIAC is an example of a _________ generation computer.

The ENIAC is an example of a _________ generation computer.

a. first
b. second
c. third
d. fourth


Answer: A

The __________ contains the 8-bit opcode instruction being executed.

The __________ contains the 8-bit opcode instruction being executed.

a. memory buffer register
b. instruction buffer register
c. instruction register
d. memory address register


Answer: C

The Patterson study examined the dynamic behavior of _________ programs, independent of the underlying architecture.

The Patterson study examined the dynamic behavior of _________ programs, independent of the underlying architecture.

a. HLL
b. RISC
c. CISC
d. all of the above


Answer: A

Architectural attributes include __________ .

Architectural attributes include __________ .

a. I/O mechanisms
b. control signals
c. interfaces
d. memory technology used


Answer: A

An I/O device is referred to as a __________.

An I/O device is referred to as a __________.

a. CPU
b. control device
c. peripheral
d. register


Answer: C

A _________ is a mechanism that provides for communication among CPU, main memory, and I/O.

A _________ is a mechanism that provides for communication among CPU, main memory, and I/O.

a. system interconnection
b. CPU interconnection
c. peripheral
d. processor


Answer: A

________ provide storage internal to the CPU.

________ provide storage internal to the CPU.

a. Control units
b. ALUs
c. Main memory
d. Registers


Answer: D

A ________ hazard occurs when there is a conflict in the access of an operand location.

A ________ hazard occurs when there is a conflict in the access of an operand location.

A. resource
B. data
C. structural
D. control


Answer: B

The ARM architecture supports _______ execution modes.

The ARM architecture supports _______ execution modes.

A. 2
B. 8
C. 11
D. 7


Answer: D

The ________ controls the movement of data and instructions into and out of the processor.

The ________ controls the movement of data and instructions into and out of the processor.

A. control unit
B. ALU
C. shifter
D. branch


Answer: A

The _________ contains the address of an instruction to be fetched.

The _________ contains the address of an instruction to be fetched.

A. instruction register
B. memory address register
C. memory buffer register
D. program counter

Answer: D

The areas between pits are called _________.

The areas between pits are called _________.

a. lands
b. sectors
c. cylinders
d. strips


Answer: A

The ________ layer is the key to the operation of Thunderbolt and what makes it attractive as a high-speed peripheral I/O technology.

The ________ layer is the key to the operation of Thunderbolt and what makes it attractive as a high-speed peripheral I/O technology.

a. cable
b. application
c. common transport
d. physical


Answer: C

The ________ contains I/O protocols that are mapped on to the transport layer.

The ________ contains I/O protocols that are mapped on to the transport layer.

a. cable
b. application
c. common transport
d. physical


Answer: B

A _________ is a PLD featuring a general structure that allows very high logic capacity and offers more narrow logic resources and a higher ration of flip-flops to logic resources than do CPLDs.

A _________ is a PLD featuring a general structure that allows very high logic capacity and offers more narrow logic resources and a higher ration of flip-flops to logic resources than do CPLDs.

a. SPLD
b. FPGA
c. PAL
d. PLA


Answer: B

The __________ are used to designate the source or destination of the data on the data bus.

The __________ are used to designate the source or destination of the data on the data bus.

a. system lines
b. data lines
c. control lines
d. address lines



Answer: D

______ increases the prefetch buffer size to 8 bits.

______ increases the prefetch buffer size to 8 bits.

a. CDRAM
b. RDRAM
c. DDR3
d. all of the above


Answer: C

RAID level ________ has the highest disk overhead of all RAID types.

RAID level ________ has the highest disk overhead of all RAID types.

a. 0
b. 1
c. 3
d. 5


Answer: B